ece353.ecs.umass.eduUMass Amherst ECE 353

ECE 353 // Computer Systems Lab I // Fall 2018. Navigation Home Schedule Instructor Office Hours and TA Lab Hours Lab Assignments Lab 1 Lab 2 Lab 3 Lab 4Verilog ResourcesQuartus II ResourcesAVR Resources Software Tools Quartus II Web Edition Software by Altera MIDI-OX MIDI Utility AVR Studio 4 by Atmel WinAVR Links UMass Amherst College of Engineering Department of Electrical and Computer Engineering University of Massachusetts, Amherst Department of Electrical and Computer Engineering ECE 353 - Computer Systems Lab I Course web site: ece353.ecs.umass.edu Course description: Design and analysis of digital systems using both hardware (Altera Complex Programmable Logic Device (CPLD) and Verilog) and software (Atmel AVR ATmega32 microcontroller, assembly language and C). Prerequisite : C or better in both ECE 232 and ECE 242 Lecture Times : Tue and Thu, 1:00PM - 2:15PM, Room: Hasbrouck 128 Instructors : Professors Holcomb and Krishna. Holcomb will be responsible for Labs 2 and 4; Krishna for Labs 1 and 3. Prof C. Mani Krishna - KEB 309 K, krishna@ecs.umass.edu, Office hours for Labs 1 & 3: Tues, Thurs 10-11 AM. Prof Daniel Holcomb - KEB 309 H, dholcomb@umass.edu Office hours for Labs 2 & 4: Tues, Thurs 10-11 AM Technical Support : Keith Shimeld - ECE Trailer, tel: 545-3523, shimeld@ecs.umass.edu Shop hours: M-F 8:30-12:00 AM and 1:30-3:30 PM, ECE Trailer, southeast of the ELab I Building, north of the Gunness Lab. Textbook : See textbook information on Spire. All handouts and course materials will be posted on the course web site TAs : see TA Lab hours link on the left Course Objectives : 1. Describe, design, and verify digital hardware using the Verilog language 2. Use the C language to simulate cache memory and the MIPS pipeline. 3. Implement digital hardware such as synchronous and asynchronous serial interfaces using programmable logic as well as microcontroller peRipherals 4. Program a microcontroller (AVR) in both assembly and C language 5. Demonstrate hardware and software-based embedded systems using a logic analyzer. 6. Work in a team, learning how to partition tasks and share responsibilities. 7. Learn to plan and manage time to get it done by a deadline 8. Document designs and the design process with formal written laboratory reports. 9. Learn key theoretical concepts in embedded and cyber-physical systems. Lab Information: Lab 1 - Simulation of a cache memory (C) Lab 2 - Design of MIDI Receiver (Verilog) Lab 3 - Simulation of the MIPS pipeline (C) Lab 4 - IR Music Box (C &/or Assembly) Embedded System Module: Material associated with this module can be found in the class moodle page. Please note that the final exam will include questions from this module. Teams: Each team will be composed of Two to Three (3) students including one team lead . The team lead is responsible for enforcing time management in the team. Each team member has to be familiar with all aspects of each project, but the team lead will need to make sure that the group starts that project in time and follows a schedule for how the work is completed. Grading: Marks are distributed as follows: Final Exam: 30% Lab 1: 10% Lab 2: 17.5% Lab 3: 25% Lab 4: 17.5% Late submission of reports will attract a penalty of 20% per day. Lab Demo, Report Schedule : See Schedule page NO ASSIGNMENTS WILL BE ACCEPTED LATER THAN FIVE DAYS AFTER THE DEADLINE. Course Format - Lectures will provide an introduction for each lab project, will introduce Quartus software, and present tutorials for Verilog HDL, AVR, and WinAVR. Software - We will issue software licenses of the Altera Quartus II and other tools for use on your personal computers at home so that you can perform most of the design and simulation work outside of the lab. The extended lab hours will be announced later. Lab Organization - Each group will be assigned a workbench drawer and a key for their kits, including breadboard and parts. Logic analyzers and additional parts that you may need will be signed out with the TA. You should not leave your breadboard or parts unlocked in the lab; you will not receive a grade for this course if the kits are not returned by the end of the semester. You may take your breadboard and components out of the lab, but essential lab equipment (oscilloscopes, logic analyzer probes, etc.) and manuals are NOT to leave the lab. Reporting Problems - Please report any problems you encounter with lab equipment, components, and breadboards to the TAs or the technician. Don’t try to fix the hardware, or just move to a different logic analyzer or stuff the bad component back into your kit and have other groups encounter the same problems as you. Please take the extra time to make sure that the equipment gets fixed or the bad component gets identified. Returning Equipment - Students take full financial responsibility for lab equipment signed out to them and understand that failure to return that equipment by the due date will result in a grade of Incomplete and possible administrative withdrawal. Simulations - It is absolutely required that you simulate your design before wiring it up, using Altera’s Quartus II simulator and other software. It is much easier to debug problems in your design through simulation than to try to find them in the prototype. This way you will spend less time in the lab, in front of a logic analyzer or oscilloscope, and more in front of a simulator on a PC at home or in the PC lab. You are required to submit a logic, block or circuit diagram (whichever appropriate) of your design with the report. Project Demonstrations - When a group demonstrates a working design, we expect all partners to fully understand the design. Every member of a group is ``jointly and severally’’ responsible for their group’s entire report and demonstration, and is expected to have detailed knowledge of the entire lab, including those parts implemented by other members of the group. All partners may not necessarily receive the same grade if it becomes clear that one has done significantly more/less work than the other(s). You should work as a team. If you are the more experienced designer/debugger in the group, we expect you to provide some patience and help to your partner(s). If you are the less experienced designer/debugger, we expect you to work extra hard to learn. Keep the Lab Clean - The Duda Hall lab will be used for Labs 2 and 4. Please keep your workplace clean and shut off all equipment (logic analyzers, printers, PCs, etc.) when you are done working on it. Please clean up wire strips, paper, etc., from your work area; nobody else will do it for you. Computer paper must be recycled, so please place it in the designated bins outside the lab. No Eating or Drinking in the Lab - Eating or Drinking in the lab is strictly prohibited. Eating or drinking in the lab is not only inappropriate, but may also cause contamination of the sensitive and expensive equipment, eventually leading to its malfunctioning. Any student caught violating this requirement will have the grade for the respective project reduced to 0 (zero). Academic Honesty - Students may discuss design and debugging problems in general terms, between groups. However, there is a fine line between discussion of the problem and discussion of the solution. Each group must independently arrive at its own solution to each project. Exchange of code, truth tables, state or gate diagrams scribbled on paper, partial or full schematics, parts of lab reports and the like is strictly forbidden and may result in your failing the course. We have access to code submitted by earlier students who took this course; as a result, we can use appropriate software tools to detect any attempt to copy from...